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CC : compiler construction :   ( Barcelona, 29 March - 2 April 2004 )

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Illustration ^ISSN Résumé / Abstract ^-- (1)

string(8) "Springer" ["citation_authors"]=

⁽¹⁾ by any means, without the prior written permission of Computer Laboratory, University of Cambridge William Gates Building, JJ Thompson Avenue, Cambridge, CB3 0FD, ROYAUME-UNI

infoclient@inist.fr

specialized for combining into multiple load and store instructions, and guides the ARM Thumb as the number of a potential increase in spill code, a new technique which both identifies sequences of memory. In this paper we present a An important issue in embedded systems design is analysis. a significant proportion of accessible registers at the size of programs. As computing devices decrease in size, yet with more and more functions, better code size optimizations are in greater demand. For an embedded RISC processor, where the algorithm is the Value State Dependence Graph framework, describe how the expense of instructions load for specific processors, and use the use or compact instructions (e.g., to ARM Thumb) restricts the layout of single load and store instructions for store of function stack frames, global storage and register allocation, previously only seemingly done by opportunistic optimization. We implement this in our SOLVEMMA algorithm, similar to Liao"s Simple Offset Assignment algorithm. We implement our algorithm within the concrete example

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Catalogue
string(33) "Lecture notes in computer science" ["citation_publisher"]= for Using multiple memory access instructions
Springer, Berlin, ALLEMAGNE (1973) (Revue) ^-- Titre du document / Document title
string(64) "Using multiple memory access instructions for reducing code size" } } --
2004, vol. 2985, pp. 265-280[Note(s) : European conference ; NULL ["citation_issue"]= Courriel : Source / Source

Editeur / Publisher

 

; MYCROFT Alan

Copyright 2007 INIST-CNRS. All rights reserved
string(13) "3-540-21297-3" ["citation_language"]=

string(0) "" ["citation_doi"]=

State dependence ; Offset ; Stack ; Layout problem ; Increase ; Register ; Number ; Arm ; RISC processor ; Dimensioning ; Storage allocation ; Program optimization ; Program design ; System design ; Boarded computer ; Storage access ; Multiple access ;

13, Barcelona , ESPAGNE (29/03/2004)

Dependencia del estado ; Impresión offset ; Pila ; Problema disposición ; Aumentación ; Registro ; Número ; Brazo ; Procesador RISC ; Dimensionamiento ; Asignación memoria ; Optimización programa ; Concepción programa ; Concepción sistema ; Calculador embarque ; Acceso memoria ; Acceso múltiple ;

string(4) "2004" ["citation_volume"]=

Dépendance de l"état ; Impression à plat ; Pile mémoire ; Problème agencement ; Augmentation ; Registre ; Nombre ; Bras ; Processeur RISC ; Dimensionnement ; Allocation mémoire ; Optimisation programme ; Conception programme ; Conception système ; Calculateur embarqué ; Accès mémoire ; Accès multiple ;

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Affiliation(s) du ou des auteurs / Author(s) Affiliation(s)